1. Technical Field
This disclosure relates to a method of fabricating semiconductor memory devices, and more particularly, to a method of fabricating static random access memory devices.
2. Discussion of Related Art
Generally, static random access memories (SRAMs) have been widely used in a field of middle-or small-sized computers because the memories operate at a high speed despite lower integration compared to dynamic random access memories (DRAMs). A conventional SRAM cell is typically composed of a flip flop circuit that includes two transfer transistors, two driver transistors, and two load elements. Information is represented as a difference in voltage between the input and output terminals of the flip flop, i.e., charges accumulated on a node of the cell. The charges are always supplemented via a PMOS transistor or a load resistor as a load element from power supply voltage (Vcc), and thus, unlike DRAMS, SRAMs need not have a refresh function.
SRAM memory cells may be further classified as either high-resistance cells that utilize a high resistance load element or as Complementary Metal Oxide Semiconductor (CMOS) cells that utilize a P-channel Metal Oxide Semiconductor (PMOS) transistor as the load element.
CMOS cells may be further classified as either thin film transistor cells that utilize a thin film transistor as the load element or as complete CMOS cells that utilize a bulk transistor as the load element.
FIG. 1 is a circuit diagram illustrating a conventional CMOS cell.
Referring to FIG. 1, the CMOS cell 100 is composed of a pair of driver transistors TD1 and TD2, a pair of transfer transistors TA1 and TA2, and a pair of load transistors TL1 and TL2. The driver transistors TD1 and TD2 and the transfer transistors TA1 and TA2 are N-channel Metal Oxide Semiconductor (NMOS) transistors while the load transistors TL1 and TL2 are both PMOS transistors.
The first driver transistor TD1 and the first transfer transistor TA1 are connected in series. A source region of the first driver transistor TD1 is connected to a ground line Vss and a drain region of the first transfer transistor TA1 is connected to a first bit line BL.
Similarly, the second driver transistor TD2 and the second transfer transistor TA2 are connected in series. A source region of the second driver transistor TD2 is connected to the ground line Vss and a drain region of the second transfer transistor TA2 is connected to a second bit line /BL. The first and second bit lines BL and /BL carry opposite information. That is, if the BL is at logic “1,”/BL is at logic “0.”
A source region of the first load transistor TL1 is connected to a power line Vcc. A drain region of the first load transistor is connected to a drain region of the first driver transistor TD1. In other words, the drains of the transistors TL1 and TD1 share a common first node.
Similarly, a source region of the second load transistor TL2 is connected to the power line Vcc and a drain region of the second load transistor is connected to a drain region of the second driver transistor TD2. In other words, the drains of the transistors TL2 and TD2 share a common second node.
A gate electrode of the first driver transistor TD1 and a gate electrode of the first load transistor TL1 are both connected to the second node. A gate electrode of the second driver transistor TD2 and a gate electrode of the second load transistor TL2 are both connected to the first node. In addition, gate electrodes of the first and second transfer transistors TA1 and TA2 are connected to a word line WL.
SRAMs may often be multi-layered to achieve high integration of semiconductor devices.
FIGS. 2A-2D are sectional diagrams illustrating a conventional method of fabricating an SRAM.
Referring to FIG. 2A, a conductive layer (not shown) is deposited on a semiconductor substrate 1. A gate line 2 is formed using by performing a photolithographic process on the conductive layer. An insulating sidewall 3 is then formed on a side surface of the gate line 2 using an etch back process.
A first insulating film 4 is formed on surface of the semiconductor substrate and on the gate line 2, and then a first interlayer insulating film 5 is formed on the first insulating film 4. The first insulating film 4 prevents diffusion of impurities in a device, such as an SRAM, and may also be used as an etch stopping layer in an etching process. The first insulating film 4 is composed of SiOn or SiN. The first interlayer insulating film 5 is an interlayer dielectric (ILD) film (oxide film).
Photoresist is then deposited on the first interlayer insulating film 5. Using exposing and developing processes, a photoresist pattern PR is formed with a uniform interval.
As shown in FIG. 2B, the first interlayer insulating film 5 and the first insulating film 4 are selectively removed using the photoresist pattern PR as a mask.
As shown in FIG. 2C, using selective epitaxial growth (SEG), a single crystalline silicon layer 8 is grown in a region 7 defined by the photoresist pattern PR.
Pre-flow of silane (SiH4) is carried out on the first interlayer insulating film 5 and the single crystalline silicon layer 8. This prevents a natural oxide film, such as silicon dioxide (SiO2), from forming on the first interlayer insulating film 5 and the single crystalline silicon layer 8.
As shown in FIG. 2D, a process temperature is elevated to a predetermined temperature and then an amorphous silicon layer 9 is deposited on the first interlayer insulating film 5 and the single crystalline silicon layer 8 using a suitable method, e.g., sputtering, plasma enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). The amorphous silicon layer 9 is annealed in order to become crystallized. The single crystalline silicon layer 8 serves as a seed for crystallization of the amorphous silicon layer 9. The crystallized silicon layer serves as channel silicon.
Unfortunately, during the annealing of the amorphous silicon layer 9, a thinning phenomenon may occur such that the resulting crystallized silicon layer has a thinned profile in a region around the single crystalline silicon layer 8.
FIG. 3 is a photograph illustrating the thinning phenomenon in which the crystallized silicon layer has a thin profile in a region 11 around a single crystalline silicon layer. This reduction in thickness of the crystallized silicon layer is undesirable because the thinner portion of the silicon layer may be removed during subsequent processes.
Embodiments of the invention address these and other disadvantages of the conventional art.